Generative AI Used to Design Chips! ! !
Since last year, the generative AI (Generative) represented by ChatGPT has stood under the spotlight of the whole world. ChatGPT can understand user input based on natural language and generate corresponding output. ChatGPT is based on large language model technology. By using massive corpus training, it can answer various questions of users and help users complete some simple tasks, including document writing and even Python code writing.
On May 10, Google released a competing product of ChatGPT at the IO conference, the PaLM 2 language model. According to Google, one of the most important user experiences of ChatGPT-like generative large language models is to help users write code, and a major feature of PaLM 2 is the support for more than 20 programming languages. Among them, for chip design engineers, the biggest highlight is that PaLM 2 supports Verilog, the most commonly used programming language in the field of digital circuit design.
It’s better to have a try than to hear about it. At present, PaLM 2 has been launched on Google’s Bard platform for public testing, so we also tried to use Bard to experience the ability of PaLM 2 to generate Verilog code. In the experiment, we asked Bard to generate two pieces of code, one piece of code is to generate a FIFO (one of the most commonly used modules in digital circuits), and the other piece of code is to generate a module that contains two previously written FIFOs , and connect the output of the first FIFO to the input of the second FIFO. The generation method is very simple, we only need to give Bard a command (prompt) based on natural language, and Bard can complete the corresponding code generation within a few seconds.
Judging from the results, the syntax of the generated code is correct, and the logic is basically correct, but the signal logic of FIFO full and empty is not completely correct (of course, the logic of FIFO full and empty is also a question that is often tested in interviews. It's not that simple to get right). In terms of code style, we can also add more hints to the command, such as "add more comments to the code", "use parameters to define the width of the interface" and so on.
In the second experiment, we mainly looked at whether Bard can reuse the previously generated modules and generate new and larger modules based on this. The instruction we use is "write a module that includes two FIFO modules you wrote earlier, and the output of the first FIFO is connected to the input of the second FIFO".
Google's PaLM 2 already has the basic Verilog code generation capability, which can generate basic modules and composite modules. Of course, the quality of its code generation needs to be improved. In addition to PaLM 2, we believe that large language models similar to ChatGPT launched by other companies may also add support for Verilog-like hardware description languages.
According to the information released by Google at the IO conference, the current chatGPT-like large language model has become an important assistant for many engineers when writing code. If we refer to the development of software development engineers in the IT field using ChatGPT-like large language models to assist in the development of code writing, we believe that large language models in the chip industry are very likely to play an important role. Here, according to the role played by the large language model in the development process, we can roughly divide it into three types of applications. The first application is to directly generate code according to the user's instructions, that is, the two examples we gave earlier in this article. The second application is to help engineers automatically complete the code when the engineer is writing the code; for example, the engineer only needs to enter the first few characters of a line of code, and the big language model can automatically help complete the code according to the context of the code, thus saving engineers development time. The third application is to help engineers analyze code and debug. Just as ChatGPT can help users optimize Python code and find bugs in code, large language models trained with relevant data can also achieve similar functions in Verilog.
Looking forward to the future, referring to the application trajectory of large language models in the IT industry, we believe that the help of large language models in chip design is expected to start with automatic code completion, because this is also the entry point of large language models in the IT industry - currently We have seen that code completion products like Github co-pilot have been applied by many IT companies to help software engineers improve programming efficiency. Relatively speaking, code completion applications have relatively low requirements for large language models. The current model has achieved a very high accuracy rate. Therefore, we expect that in the field of chip design, there will also be applications based on large language models in the Verilog field. The code completion tool of Google will soon appear to help engineers improve efficiency (it is estimated that Google's internal chip team has already begun to use similar tools).
After code completion, with the further development of large language models, large language models that automatically generate code according to user instructions will also be more and more used. From the current point of view, this kind of code generation application needs to be further integrated with the entire project development process-whether this kind of code automatic generation application is most suitable for the writing of the underlying modules, or for the generation of integration between the upper modules? Further exploration is needed, but in any case, ChatGPT has amazing potential in the field of automatic code writing. It can complete the code that takes hours to write manually in a few seconds. Such efficiency improvement will undoubtedly bring benefits to the entire industry and the chip development process. Come revolutionary change.
At present, ChatGPT-like large language models have achieved very good results in code writing in popular programming languages such as Python, which proves that large language models can realize automatic code writing, completion and debugging in theory and engineering. of. The main reason why Google's PaLM 2's support for Verilog still needs to be further improved, we think, is that the amount of training data is not enough. From the perspective of the amount of training data, there are a large number of open source Python codes available on the Internet for training large language models to complete high-quality code generation, but the amount of Verilog codes available for training large language models on the Internet is more popular than Python, etc. In terms of language, it may be several orders of magnitude less. It's not that the number of Verilog codes written by humans is not enough, but that the vast majority of Verilog codes are not open source, but the intellectual property rights of chip companies. For example, Google is unlikely to obtain Qualcomm's Verilog codes when training PaLM. Who will take the lead in developing large language models in the field of chip design in the future? We believe there are several forces that cannot be ignored:
The first is large technology companies with full-stack technology capabilities. These companies not only have the ability to develop large language models, but also have successful chip businesses, including Google in the United States and Huawei in China. From a technical point of view, these companies have accumulated a large amount of Verilog-related codes for training large language models, and from a business point of view, these companies also have the drive to use large language models to improve the efficiency of chip design teams.
Followed by EDA giants, including Synopsys, Cadence and so on. These EDA companies have a strong business drive and a sense of urgency, because the big language model AI will indeed become the next revolutionary change in the EDA industry, and whoever takes the lead in this field will gain an advantage in the next generation of EDA competition; from In terms of technology accumulation, these companies have good AI model capabilities, and at the same time have a large amount of Verilog code data for training models (because these EDA companies have quite successful IP business, they have accumulated enough high-level experience while developing these IPs. quality code data).
Finally, the power of the open source community cannot be ignored. From the perspective of large language models, the open source community has done a lot of meaningful exploration on the basis of CahtGPT and open source LLAMA language models. In addition, with the increase of open source projects such as RISC-V, the amount of data owned by the open source community will also increase. more. We expect the open source community to have the opportunity to realize some small and beautiful novel applications based on large language models, which can also promote the technical development of the entire large language model in the field of chip design.
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