Xilinx's Partial Reconfiguration Technology (Partial Reconfiguration)
Partial reconfiguration technology (Partial Reconfiguration) is a part of the field programmable gate array device, which refers to the partial reconfiguration of FPGA while other parts are still running normally.
As we all know, hardware can also be designed in a modular manner like software. For example, use HDL to create sub-modules inside the FPGA device, and then use higher-level modules to encapsulate various sub-modules.
Typically, reconfiguring an FPGA requires placing it in reset and reloading a new design into the device via an external controller. Partial reconfiguration technology allows a controller inside or outside the FPGA to load a partial design into a reconfigurable module while other parts of the design continue to work normally. Partial reconfiguration can also be used to save space when storing multiple designs. For example, only different parts between multiple designs are stored, and the same part of the design is only saved once and will not be saved repeatedly.
To give a common example, for example, in communication products, if an FPGA device controls multiple connections, some connections may need to be encrypted, and different encrypted IP cores must be loaded to handle different connections. Down the entire controller to switch.
At present, partial reconfiguration technology cannot support all FPGA product series under XILINX. Only Virtex II, Virtex II Pro, and Virtex 4 series are supported in the current version of the software, and newer product series should be supported in newer software versions. A special software flow should be emphasized during this module design process. Typically, such design blocks are built on well-defined boundaries within the FPGA and require special design to map them to the internal hardware.
In terms of design functionality, partial reconfiguration can be divided into the following two types:
Dynamic partial reconfiguration (dynamic partial reconfiguration), obviously, this is an active reconfiguration that allows other parts of the FPGA to change part of the device while it is still running normally.
static partial reconfiguration during which the device is not active. While part of the data is being sent into the FPGA, the rest of the device is stopped (in shutdown mode), and the rest of the device starts running after configuration is complete.
The partial reconfiguration of FPGA devices of XILINX can also be divided into the following two types:
Module-based partial reconfiguration allows reconfiguration of specific module elements in a design. To ensure communication across reconfigurable block boundaries, a special bus macrocell needs to be prepared in advance. The bus macrocell works as a fixed routing bridge connecting reconfigurable blocks in spare parts of the design. Module-based partial reconfiguration needs to run a specific set of Guidelines during the design specification phase. Ultimately create a separate bitstream for each reconfigurable block in the design. Such a bit stream can then be used to perform partial reconfiguration.
Difference-based partial reconfiguration can be used with a small modification to the design. Especially useful when changing LUT equations or memory block contents. Such partial bit streams contain only the difference information between the existing design structure and the new structure. There are two approaches to difference-based partial reconfiguration: front-end and back-end. The front-end approach is based on modifications of the Hardware Description Language (HDL). This approach is clear for a solution that requires a full iterative synthesis and implementation process. The back-end approach allows modifications to be made during the implementation phase of prototyping, so there is no need to re-execute the synthesis process. The use of both methods will create a partial bit stream, and can be used for the partial reconfiguration function of the FPGA.
It should be noted that partial reconfiguration can only update a part of the FPGA. No part of the FPGA is required to continue running during the update.
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